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    Explore Pybytes | Official Documentation | Report a Firmware Bug/Issue | GitHub

    Disable wifi for low power operation

    Scheduled Pinned Locked Moved LoPy
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    • T Offline
      tmk854
      last edited by

      Is it possible to disable the wifi radios for lora-only operation?

      I guess I could try to put the Lopy into WLAN.STA mode and not connect to anything:

      wlan = network.WLAN(mode=WLAN.STA)

      but I'm not sure that would be equivalent to disabled hardware.

      A 1 Reply Last reply Reply Quote 1
      • A Offline
        abilio @tmk854
        last edited by

        @tmk854, this option is currently not available, but it will be added in a future firmware release. I invite you to stay tuned to upcoming news.

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        • M Offline
          madsdk
          last edited by

          Are there any news about this feature? I'm deploying some LoRa prototypes in a couple of days, and I'd like them to be able to run for a long time out in the wild ;)

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          • bmarkusB Offline
            bmarkus
            last edited by bmarkus

            In a typical LoRaWAN scenario there are 'A-Class' devices, sending sensor data in every 10 minutes, hour or less. These are in deep sleep between two measurement/transmission period. This way you can save battery. Just disabling WiFi without going to sleep doesn't help too much. Also reduction of clock can help but as far as I see it is not yet supported and do not know what ESP32 supports itself as a minimum clock frequency.

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            • L Offline
              livius
              last edited by livius

              from ESP documentation

              3.3 System Clocks
              3.3.1 CPU Clock
              Upon reset, an external crystal clock source (2 MHz ~ 60 MHz), is selected as the default CPU clock. The external
              crystal clock source also connects to a PLL to generate a high frequency clock (typically 160 MHz).
              
              In addition to this, ESP32 has an internal 8 MHz oscillator, of which the accuracy is guaranteed by design and
              is stable over temperature (within 1% accuracy). Hence, the application can then select from the external crystal
              clock source, the PLL clock or the internal 8 MHz oscillator. The selected clock source drives the CPU clock,
              directly or after division, depending on the application.
              

              think about people first, then computers

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