Sharing SPI with Lora on fipy
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The fipy has one SPI bus and it is in use by Lora on pins P5, P6 and P7 (and internal gpio18 and gpio23) according to the pinout.
Can I share this bus using another chip select pin or is the Lora bus on a separate thread or interrupt driven and it can only be used with Lora completely deactivated?
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